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| S3C380D/F380D PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW Samsung S3C380D 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for TV applications. Among the outstanding features of the S3C380D is its CPU core, a 16/32-bit RISC processor (ARM7TDMI) designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general-purpose microprocessor macro-cell that was developed for use in application-specific and customer-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. The S3C380D was developed using the ARM7TDMI core, CMOS standard cell, and a data path compiler. Most of the on-chip function blocks were designed using an HDL synthesizer. The S3C380D has been fully verified in the Samsung ASIC test environment. By providing a complete set of common system peripherals, the S3C380D minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: * * * * * * * * * * * * 4-Kbyte RAM (3008-byte (1504 x 16 bits) general register and 1088-byte (544 x 16 bits) OSD/CCD RAM) 128-Kbyte internal program memory Two 14-bit PWM modules Three 16-bit timers On screen display module Crystal/Ceramic oscillator or external clock can be used as the clock source Standby mode support: SLEEP mode One 8-bit basic timer and 3-bit watchdog timer Interrupt controller (16 interrupt sources and 2 vectors) Five 4-bit ADCs Four programmable I/O ports 42-pin SDIP 1-1 PRODUCT OVERVIEW S3C380D/F380D FEATURES CPU * ARM7T CPU core A/D converter * 5-channel: 4-bit conversion resolution (flash ADC) Memory * * 4-Kbyte RAM (3008-byte general purpose register area + 1088-byte OSD/CCD RAM) 128 Kbyte internal program memory Remocon receiver * * FIFO 8 steps FIFO interrupt is full (8) step overflow On screen display (OSD) mode General I/O * Four I/O ports (25 pins total) (6 V O/D: 3 pins, 5 V O/D: 4 pins) * * * * * * Analog level OSD Halftone 64 character colors 16 different character sizes Graphic OSD S/W CCD Basic timer and watchdog timer * * 8-bit counter + 3-bit counter Overflow signal of 8-bit counter makes a basic timer interrupt and control the oscillation warm-up time Overflow signal of 3-bit counter makes a system reset Oscillator frequency * * * * 32,768 Hz external crystal oscillator 1 Hz generation for real time clock PLL (Phase Lock Loop) controlled oscillators Maximum 16 MHz CPU clock * Timer/Counters * Three general purpose 16-bit timer/counters with interval timer modes Operating temperature Range Interrupts * * * 16 interrupt sources and 2 vectors Fast interrupt processing 2 interrupt shadow registers (32 bit x 2) * - 20 C to + 85 C Operating Voltage Range * 4.5 V to 5.5 V Pulse width modulation (PWM) module * 14-bit PWM with 2-channel PWM counter Package Type * 42-pin SDIP 1-2 S3C380D/F380D PRODUCT OVERVIEW BLOCK DIAGRAM ADC0-ADC4 4-Bit ADC System Control & PLL VDD, VSS XIN XOUT RESET LPF ARM7TDMI 16-Bit RISC CPU Core Port0 Port1 Port2 Port3 OSD & CCD Ext. Interrupt INT0-INT3 P0.0-P0.7 P1.0-P1.7 P2.0-P2.7 P3.0 PWM0 PWM1 14-Bit PWM 16-Bit Timer/Counter 2 RAM 3008 Byte Remocon Receive ROM 128 Kbyte IRIN OSD/CCD RAM 1088 byte 16-Bit Timer/Counter 0 Watchdog Timer 16-Bit Timer/Counter 1 Figure 1-1. S3C380D Block Diagram 1-3 PRODUCT OVERVIEW S3C380D/F380D PIN ASSIGNMENTS P0.0/PWM0 P0.1/PWM1 P0.2 P1.0 P1.1 P1.2 P1.3 P1.4/ADC1 P1.5/ADC2 P1.6/ADC3 P1.7/ADC4 VDD1 VSS1 P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4 P2.5 P2.6 P2.7/OSDHT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C380D (42-SDIP-600) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.3 P0.4 P0.5 P0.6 P0.7 VSS2 VPP P3.0 VDD2 VSS XOUT VSS VSS3 LPF CVI IN (ADC0) V-Sync H-Sync Vblank Vred Vgreen Vblue Figure 1-2. S3C380D Pin Assignments (42-SDIP) 1-4 S3C380D/F380D PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C380D Pin Descriptions Pin Name P0.0 Pin Type I/O Pin Description Input mode or push-pull output mode is software configurable. P0.0: PWM0 (14-bit PWM Output) General I/O Port (3-bit), Input or n-channel open-drain output is software configurable. Pins can withstand up to 6-volt loads. An alternative function is supported. P0.1: PWM1 (14-Bit PWM Output) General I/O Port (4-bit), Input or Output mode (push-pull or n-channel open drain) is software configurable. I/O Input/output mode or push-pull output mode is software configurable. General I/O Port (4-bit), configurable for digital input or n-channel open drain output. P1.4-P1.7 can withstand up to 5-volt loads. Multiplexed for alternative use as external inputs ADC1-ADC4. I/O General I/O Port (4-bit), input or push-pull output mode is software configurable. Multiplexed for alternative use as external interrupt inputs INT0-INT3. Input mode or push-pull output mode is software configurable. An alternative function is supported. P2.7: OSDHT (Halftone signal output) Input mode or push-pull output mode is software configurable. Output pin for 14-bit PWM0 circuit Output pin for 14-bit PWM1 circuit Input for 4-bit resolution flash A/D Converter External interrupt input pins Halftone control signal output for OSD Remocon signal input Normal mode: Remocon signal input OTP Write mode: VPP=12.5 V Video signal input Circuit Type 6 Pin Numbers 1 Share Pins PWM0 P0.1-P0.2 P0.3 3 2-3 42 PWM1 P0.4-P0.7 7 38-41 P1.0-P1.3 P1.4-P1.7 6 4 4-7 8-11 ADC1ADC4 P2.0-P2.3 2 14-17 INT0-INT3 P2.4-P2.7 I/O 6 18-21 OSDHT P3.0 PWM0 PWM1 ADC1-4 INT0-INT3 OSDHT IRIN I/O O O I I O I 6 6 3 4 2 6 1 35 1 2 8-11 14-17 21 36 P0.0 P0.1 P1.4-7 P2.0-3 P2.7 - CVI IN I 8 28 ADC0 1-5 PRODUCT OVERVIEW S3C380D/F380D Table 1-1. S3C380D Pin Descriptions (Continued) Pin Name RESET Pin Type I - I I O O O O I - PLL filter pin Pin Description System reset input pin H-sync input for OSD and CCD V-sync input for OSD and CCD Video blank signal output for OSD and CCD Red signal output for OSD and CCD Green signal output for OSD and CCD Blue signal output for OSD and CCD Input for 4-bit resolution flash A/D Converter (1.5V-2.0V) Power supply pins Circuit Type 9 - 1 1 5 5 5 5 8 - Pin Numbers 33 29 26 27 25 24 23 22 28 12, 34 13, 37 30 31,32 Share Pins - - - - - - - - CVI IN - LPF H-SYNC V-SYNC Vblank Vred Vgreen Vblue ADC0 VDD1, VDD2 VSS1, VSS2 VSS3 XIN, XOUT I, O System clock pins (32,768 Hz) - - 1-6 S3C380D/F380D PRODUCT OVERVIEW PIN CIRCUITS In Schmitt Trigger Input Noise Filter Figure 1-3. Pin Circuit Type 1 (H-Sync, V-Sync, IRIN) VDD Data In/Out Output DIsable Schmitt Trigger Input Input INT Noise Filter Figure 1-4. Pin Circuit Type 2 (P2.0-P2.3, INT0-INT3) 1-7 PRODUCT OVERVIEW S3C380D/F380D In/Out Data Input Schmitt Trigger Input NOTE: Circuit type 3 can withstand up to 6 V loads. Figure 1-5. Pin Circuit Type 3 (P0.1-P0.3, PWM1) In/Out Data Input Schmitt Trigger Input A/D IN NOTE: Circuit type 4 can withstand up to 5 V loads. Figure 1-6. Pin Circuit Type 4 (P1.4-P1.7, ADC1-ADC4) 1-8 S3C380D/F380D PRODUCT OVERVIEW VDD Data In/Out Figure 1-7. Pin Circuit Type 5 (Vblue, Vgreen, Vred, Vblank) VDD Data In/Out Output DIsable Input Schmitt Trigger Input Figure 1-8. Pin Circuit Type 6 (P0.0, P1.0-P1.3, P2.4-P2.7, P3.0, OSDHT, PWM0) 1-9 PRODUCT OVERVIEW S3C380D/F380D VDD Data In/Out Open-drain Output DIsable Input Schmitt Trigger Input Figure 1-9. Pin Circuit type 7 (P0.4-P0.7) In A/D Input Figure 1-10. Pin Circuit type 8 (CVI IN, ADC0) VDD 50 K In Noise Filter Schmitt Trigger Input Figure 1-11. Pin Circuit type 9 (RESET) 1-10 S3C380D/F380D PRODUCT OVERVIEW CPU CORE OVERVIEW The S3C380D CPU core is the ARM7TDMI processor, a general purpose, 32-bit microprocessor developed by Advanced RISC Machines, Ltd. (ARM). The core's architecture is based on Reduced Instruction Set Computer (RISC) principles. The RISC architecture makes the instruction set and its related decoding mechanisms simpler and more efficient than with microprogrammed Complex Instruction Set Computer (CISC) systems. The resulting benefit is high instruction throughput and impressive real-time interrupt response. Pipelining is also employed so that all components of the processing and memory systems can operate continuously. The ARM7TDMI has a 32-bit address bus. An important feature of the ARM7TDMI processor, differentiating it from the ARM7 processor, is a unique architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture and consists of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, but have been re-coded using 16-bit wide opcodes. Because THUMB instructions are one-half the bit width of normal ARM instructions, they produce very highdensity code. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a normal 32-bit instruction. In other words, the Thumb architecture gives 16-bit systems a way to access the 32-bit performance of the ARM core without incurring the full overhead of 32-bit processing. Because the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit Thumb instructions, it lets you mix routines of Thumb instructions and ARM code in the same address space. In this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application. Address Register Address Register Instruction Decoder and Logic Control Register Bank Multiplexer Barrel Shifter Instruction Pipeline and Read Data Register 32-Bit ALU Write Data Register Figure 1-12. ARM7TDMI Core Block Diagram 1-11 PRODUCT OVERVIEW S3C380D/F380D INSTRUCTION SET The S3C380D instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit THUMB instruction set. The 32-bit ARM instruction set is comprised of thirteen basic instruction types which can, in turn, be divided into four broad classes: * * * Four types of branch instructions which control program execution flow, instruction privilege levels, and switching between ARM code and THUMB code. Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). Three types of load and store instructions which control data transfer between memory locations and the registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. Three types of co-processor instructions which are dedicated to controlling external co-processors. These instructions extend the off-chip functionality of the instruction set in an open and uniform way. NOTE All 32-bit ARM instructions can be executed conditionally. * The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction set. The THUMB instructions can be divided into four functional groups: * * * * Four branch instructions. Twelve data processing instructions, which are a subset of the standard ARM data processing instructions. Eight load and store register instructions. Four load and store multiple instructions. NOTE Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the identical processing model. The 32-bit ARM instruction set and the 16-bit THUMB instruction sets are good targets for compilers of many different high-level languages. When assembly code is required for critical code segments, the ARM programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. Pipelining is employed so that all parts of the processor and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. 1-12 S3C380D/F380D PRODUCT OVERVIEW OPERATING STATES From a programmer's point of view, the ARM7TDMI core is always in one of two operating states. These states, which can be switched by software or by exception processing, are: * * ARM state (when executing 32-bit, word-aligned, ARM instructions), and THUMB state (when executing 16-bit, half-word aligned THUMB instructions). OPERATING MODES The ARM7TDMI core supports seven operating modes: * * * * * * * User mode: the normal program execution state FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel process IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling Supervisor mode: a protected mode for the operating system Abort mode: entered when a data or instruction pre-fetch is aborted System mode: a privileged user mode for the operating system Undefined mode: entered when an undefined instruction is executed Operating mode changes can be controlled by software, or they can be caused by external interrupts or exception processing. Most application programs execute in User mode. Privileged modes (that is, all modes other than User mode) are entered to service interrupts or exceptions, or to access protected resources. 1-13 PRODUCT OVERVIEW S3C380D/F380D REGISTERS The S3C380D CPU core has a total of 37 registers: 31 general-purpose, 32-bit registers, and 6 status registers. Not all of these registers are always available. Which registers are available to the programmer at any given time depends on the current processor operating state and mode. NOTE When the S3C380D is operating in ARM state, 16 general registers and one or two status registers can be accessed at any time. In privileged mode, mode-specific banked registers are switched in. Two register sets, or banks, can also be accessed, depending on the core's current state: the ARM state register set and the THUMB state register set: * The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for R15, are for general-purpose use, and can hold either data or address values. An additional (seventeenth) register, the CPSR (Current Program Status Register), is used to store status information. The THUMB state register set is a subset of the ARM state set. You can access eight general registers, R0R7, as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (SPSR). * The THUMB state registers are related to the ARM state registers as follows: * * * THUMB state R0-R7 registers and ARM state R0-R7 registers are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP, LR, and PC map directly to ARM state registers R13, R14, and R15, respectively In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for assembly language programming and use them for fast temporary storage, if necessary. 1-14 S3C380D/F380D PRODUCT OVERVIEW EXCEPTIONS An exception arises whenever the normal flow of program execution is interrupted. For example, when processing must be diverted to handle an interrupt from a peripheral. The processor's state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. Multiple exceptions may arise simultaneously. To process exceptions, the S3C380D uses the banked core registers to save the current state. The old PC value and the CPSR contents are copied into the appropriate R14 (LR) and SPSR register. The PC and mode bits in the CPSR are forced to a value which corresponds to the type of exception being processed. The S3C380D core supports seven types of exceptions. Each exception has a fixed priority and a corresponding privileged processor mode, as shown in Table 1-2. Table 1-2. S3C380D CPU Exceptions Exception Reset Data abort FIQ IRQ Prefetch abort Undefined instruction Software interrupt Mode on Entry Supervisor mode Abort mode FIQ mode IRQ mode Abort mode Undefined mode Supervisor mode Priority 1 (Highest) 2 3 4 5 6 (Lowest) 6 (Lowest) 1-15 S3C380D/F380D ELECTRICAL DATA 17 OVERVIEW (TA = 25C) Parameter Supply voltage Input voltage ELECTRICAL DATA This chapter describes the S3C380D electrical data. Information is presented according to the following Table of Contents: Table 17-1. Absolute Maximum Ratings Symbol VDD VI1 VI2 Conditions Rating - 0.3 to + 7.0 Unit V V P0.1-P0.3, P1.4-P1.7 (open-drain) All ports except VI1 All output ports One I/O pin active All I/O pins active - 0.3 to + 6 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 10 - 50 + 20 + 100 - 20 to + 85 - 40 to + 125 Output voltage Output current high Output current low VO I OH V mA I OL TA TSTG One I/O pin active Total pin current for ports 0, 1, 2, and 3 mA C C Operating temperature Storage temperature - - 17-1 ELECTRICAL DATA S3C380D/F380D Table 17-2. D.C. Electrical Characteristics (TA = - 20C to + 85C, VDD = 4.5 V to 5.5 V) Parameter Input high voltage Input low voltage Symbol VIH1 VIH2 VIL1 VIL2 Output high voltage VOH1 VOH2 Output low voltage VOL1 VOL2 VOL3 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current ILOH1 ILOH2 Conditions All input pins except VlH2 RESET Min 0.8 VDD 0.85 VDD - Typ - Max VDD Unit V All input pins except VIL2 RESET - 0.2 VDD 0.15 VDD V Vblank, P2.4, P2.5 IOH = - 1 mA All ports except VOH1 IOH = - 500 uA P2.4, P2.5 IOL = 15 mA All ports except VOL1, VOL3 IOL = 2 mA Vblank IOL = 1 mA VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XOUT VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN, XOUT VOUT = VDD All output pins except ILOH2 VOUT = 6 V P0.1-P0.3, P1.4-P1.7 (N-channel, open-drain) VOUT = 0 V All output pins VDD- 1.0 VDD- 0.5 - - - V - 1.0 0.4 0.4 V - 3 - -3 - - 1 20 uA - -1 -- 20 uA - 1 10 uA Output low leakage current ILOL - - -1 uA 17-2 S3C380D/F380D ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 4.5 V to 5.5 V) Parameter Pull-up resistor Supply current Symbol RP2 IDD1 IDD2 Conditions VIN = 0 V RESET only VDD = 5 V 16 MHz CPU clock Sleep mode Min 30 - Typ 50 50 0.5 Max 70 100 1 Unit K mA Table 17-3. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Interrupt input high, low width RESET input low Symbol tINTH, tINTL tRSL tVW tHW tNF1 tNF4 tNF3 tNF2 Conditions Ports 2.0-2.3 Input - - P2.0-P2.3 Glitch filter (oscillator block) RESET Min - - 4 3 - Typ 300 1000 - - 300 1000 1000 300 Max - - - - - Unit ns ns s s ns width V-sync pulse width H-sync pulse width Noise filter H-sync, V-sync tINTL tRSL 0.8 VDD 0.2 VDD tINTH Figure 17-1. Input Timing measurement points 17-3 ELECTRICAL DATA S3C380D/F380D Table 17-4. Input/Output Capacitance (TA = - 40 C to + 85 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are returned to VSS Min - Typ - Max 10 Unit pF Table 17-5. Data Retention Supply Voltage in Sleep Mode (TA = - 20 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Sleep mode Sleep mode VDDDR = 5.0 V Min 2 - Typ - - Max - 2 Unit V mA RESET Occurs Oscillation Stabilization Time Normal Operting Mode ~ ~ ~ ~ SLEEP Mode Data Retention Mode VDD VDDDR Execution of Sleep Operation RESET tWAIT Figure 17-2. Sleep Mode Release Timing When Initiated by RESET 17-4 S3C380D/F380D ELECTRICAL DATA Table 17-6. Oscillator Frequency (TA = - 20 C + 85 C) Oscillator Crystal or ceramic Clock Circuit C1 XIN S3C380D XOUT XIN S3C380D Test Condition VDD = 4.5 V to 5.5 V C1 = C2 = 33 pF recommended Min - Typ 32,768 Max - Unit Hz C2 External clock VDD = 4.5 V to 5.5 V - 32,768 - Hz XOUT Table 17-7. Oscillator Clock Stabilization Time (TA = - 20 C + 85 C, VDD = 4.5 V to 5.5 V) Oscillator Crystal External clock Oscillator stabilization time XIN = 32,768 Hz XIN input high and low level width (tXH, tXL) tWAIT when released by a reset, XIN = 32,768 Hz tWAIT when released by a interrupt (note) Test Condition Min - 15 - - Typ - - - - Max 20 125 500 4 Unit ms ns ms ms NOTE: The duration of the oscillator stabilization time, tWAIT, when it is released by an interrupt, is determined by the settings in the basic timer control register, BTCON. 17-5 ELECTRICAL DATA S3C380D/F380D Table 17-8. A/D Converter Electrical Characteristics (TA = - 20 C to + 85 C, VDD = 4.5 V to 5.5 V (ADC1-ADC4), VDD = 5.0 V (ADC0)) Parameter Resolution Absolute accuracy (1) Conversion Time (2) Analog input voltage Analog input impedance Analog output impedance Symbol - - Conditions - CPU clock = 16 MHz ADC0 ADC1-4 tCON VIAN CPU clock = 16 MHz - ADC1-4 ADC0 RAN ROAN - CPU clock = 16 MHz Conversion time = 4 MHz CPU clock = 16 MHz Conversion time = 0.5, 1, and 2 MHz Min - - - - AVSS 1.5 2 - - Typ - - - (3) Max 4 1.0 0.5 - AVREF 2.0 - 5 10 Unit Bit LSB LSB ns V V M K K - - - - - NOTES: 1. Excluding quantization error, absolute accuracy values are within 1 LSB (ADC0), 0.5 LSB (ADC1-4) 2. `Conversion time' is the time required from the moment a conversion operation starts until it ends 3. ADC conversion time is controled by ADCON.9-.8. 17-6 S3C380D/F380D MECHANICAL DATA 18 OVERVIEW #42 14.00 0.2 MECHANICAL DATA The S3C380D microcontroller is currently available in 42-pin SDIP (42-SDIP-600) package. #22 0-15 #1 #21 39.10 0.2 (1.77) 1.00 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 18-1. 42-Pin SDIP Package Dimensions 0.51 MIN 3.30 0.3 0.50 0.1 3.50 0.2 39.50 MAX 5.08 MAX 0.2 5 +0 - 0 .1 .05 42-SDIP-600 15.24 18-1 S3C380D/F380D S3F380D MTP 19 OVERVIEW S3F380D MTP The S3F380D single-chip CMOS microcontroller is the MTP (Multiple Time Programmable) version of the S3C380D microcontroller. It has an on-chip Flash ROM instead of a masked ROM. The flash ROM is accessed by serial data format. The S3F380D is fully compatible with the S3C380D, both in function and pin configuration. P0.0/PWM0 P0.1/PWM1 SCLK/P0.2 SDAT/P1.0 P1.1 P1.2 P1.3 P1.4/ADC1 P1.5/ADC2 P1.6/ADC3 P1.7/ADC4 VDD/VDD1 VSS/VSS1 P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4 P2.5 P2.6 P2.7/OSDHT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3F380D (42-SDIP-600) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.3 P0.4 P0.5 P0.6 P0.7 VSS2/VSS IRIN/VPP P3.0 VDD2/VDD RESET/RESET XOUT XIN VSS3/VSS LPF CVI IN (ADC0) V-sync H-sync Vblank Vred Vgreen Vblue Figure 19-1. S3F380D Pin Assignment (42-SDIP) 19-1 S3F380D MTP S3C380D/F380D Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM (S3F380D) Main Chip Pin Name P1.0 (Pin 4) Pin Name SDAT Pin No. 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (Input only pin) 0-5 V: operating mode 12.5 V: MTP mode 5 V: operating mode, 0 V: MTP mode Logic power supply pin. P0.2 (Pin 3) IRIN RESET SCLK VPP RESET 3 36 33 12/34, 13/30/37 I/O I I I VDD/VSS VDD/VSS Table 19-2. Comparison of S3F380D and S3C380D Features Characteristic Program Memory Operating Voltage (VDD) MTP Programming Mode Pin Configuration Flash ROM programmability 4.5 V to 5.5 V VDD = 5 V, VPP = 12.5 V 42 SDIP User program under 100 time 42 SDIP Programmed at the factory S3F380D 128-Kbyte Flash ROM S3C380D 128-Kbyte mask ROM 4.5 V to 5.5 V - 19-2 |
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